With the increasing miniaturization of semiconductor elements in recent years, a demand has risen for technologies to achieve the following: reduction of the gate length of the transistor, reduction of the thickness of the gate oxide film, reduction of the film thickness of the electrode side wall spacer, and shallowing of junctions. However, it has also been desirable for basic device properties such as diffusion resistance, electrode resistance, and parasitic capacitance to be reduced or held at the level of the current generation.
Regarding processes currently under development, 0.13-μm processes require diffusion layers of depths from 45 to 90 nm and 0.1 μm processes require diffusion layers of depths from 35 to 70 nm. Meanwhile, the resistance required for the diffusion layer and gate wiring is 4 to 6 Ω. Currently, the most widely used silicide in 0.13-μm processes is CoSi2 and the specific resistance is from 18 to 28 μΩ-cm.
Consequently, a CoSi2 film thickness of approximately 36 nm is required to obtain a sheet resistance of 5 Ω, and the corresponding reaction quantity of Si is 130 nm. Even if Ni, having a resistance of 12 to 15 μΩ-cm, which is a lower specific resistance than Co, is used, 24 nm of Ni silicide is required, and thus 44 nm of Si is required for the reaction (IEDM 84 P110)
As a result, the distance between the junction surface of the diffusion layer and the bottom surface of the silicide layer decreases and leads to degradation of the junction properties (increased junction leakage current). The distance between the junction and the bottom surface of the silicide maintains the junction properties, and based on experience it is generally determined that a distance of approximately 50 nm is required. On the other hand, it is desirable to make the diffusion layer shallower in order to miniaturize the transistor. Thus, the objectives of maintaining the silicide resistance value and developing a more miniature transistor have a reached an impasse where they contradict each other.
One means of solving this problem was to use stacked diffusion layer technology as discussed in Laid-Open Japanese Patent Publication No. 7-22338. Using such technology, Si is stacked onto a diffusion layer region, high-concentration ion implantation is conducted, and then a silicide is formed. This conventional art manufacturing method will be further described with regard to FIGS. 16–19.
FIG. 16 depicts the formation of an isolation region 102 on a silicon substrate 101. Impurities are implanted into the substrate 101 as necessary. Gate oxide film 103 and gate electrode 104 are deposited, and patterning is conducted. Next, as shown in FIG. 17, a drain extension region 106 is formed by conducting drain extension, pocket implantation, etc. Then a side wall spacer 105 is formed by depositing an insulating film on the entire surface and conducting an anisotropic etch. Next, as shown in FIG. 18, a silicon film 107 is epitaxially grown on silicon substrate 101 using an epitaxial method such as the load-lock type silicon CVD device described in Laid-Open Japanese Patent Publication No. 7-22338. Thereafter, ion implantation is conducted to form a high-concentration region.
In conventional processes having no epitaxial region, it was necessary to conduct extremely shallow implantation in order to improve the transistor characteristics. However, when there is an epitaxially grown region on the silicon substrate as shown in FIG. 18, a higher implantation energy could be used and a heat treatment with sufficient activation could be conducted. In short, as shown in FIG. 19, a sufficiently deep junction 108 could be made and the transistor characteristics could be improved.
However, these stacked diffusion layer technologies, like those presented in Laid-Open Japanese Patent Publication No. 7-22338, increase the parasitic capacitance between the gate electrode and the diffusion layer, and have an enormous effect on the speed of the circuit itself. Also, it is necessary to lower the resistance of the drain extension in order to raise the drive current of the transistor. As a result, it is necessary to make the side wall spacer of the gate electrode thinner, which causes the parasitic capacitance to increase even further.
The parasitic capacitance of the gate side wall can be calculated as indicated below. Assuming the width of the transistor channel is Wch, the width of the side wall is Wsw, the side wall material is Si3N4, and the height of the stacked diffusion layer is d, then the parasitic capacitance CSW generated in one transistor is given byCSW=∈0*∈SiN*d*Wch/Wsw.
Here, ∈0 is the relative dielectric constant in a vacuum (8.85×10−12 F/m) and ∈ SiN is the relative dielectric constant (7.5) of the nitride film. It is clear that the parasitic capacitance increases when the width of the side wall is made thinner and when the stacked diffusion layer is made thicker.
The dielectric constant of SiO2 is lower than that of Si3N4. SiO2 has a dielectric constant of 3.9, but Si3N4 has a dielectric constant of 7.5. See S. M. Sze, Physics of Semiconductor Devices, 2nd Ed., page 852. Silicon oxynitrides have dielectric constants ranging between about 4 and 7. In contrast, other nitrides have higher dielectric constants, where GaN has a dielectric constant of about 8.9, AlN has a dielectric constant of about 8.5 and InN has a dielectric constant of about 15.3. Also, the dielectric constants of metal oxides can be considered, where Al2O3 has a dielectric constant of about 9, Ta2O5 has a dielectric constant of about 25, ZrO2 has a dielectric constant of about 25, HfO2 has a dielectric constant of about 40 and TiO2 has a dielectric constant of about 50.
As has been noted, conventional technology for the manufacture of thin film transistors has disadvantages when applied to further miniaturization.